Advanced Oxide Materials and Devices Project Leader: Alex Ignatiev at ignatiev@uh.edu
Task Leader:Professor Nai Juan Wu at naijwu@uh.edu

A major challenge in DRAM development for the Giga-bit scale and beyond, is to integrated high dielectric oxide capacitors with silicon, and to make them three dimensional at the sub-micro feature size. High dielectric SrTiO3 (STO) and BaSrTiO3 (BST) films have been integrated with silicon through a unique Ni/TiN buffer layer. The films have been deposited by photo-assisted MOCVD (PhAMOCVD) as well as pulsed laser deposition. The dielectric constants of ~500 with leakage currents of less than 10-6 A/cm2 in the field range of 2x105 V/cm have been achieved for BST thin films of thickness ~100nm. BST oxide films of less than 50nm thickness show dielectric constants of ~150 - 200. 3-D test structure capacitors have been fabricated on silicon by reactive ion etching of the TiN/Ni buffer layefrs, followed by MOCVD deposition of BST films. Good sidewall coverage has been achieved with scaling studies underway for submicron structured 3-D capacitors.

Personnel:
Dr. Yimin Chen: Research Scientist
Kyuho Cho: Research Assistant
Shangqing Liu: Research Scientist

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